Methodologies for Adaptation to Process Variations, Manufacturing Defects, and Transient Errors in Scaled CMOS

VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With CMOS device dimensions falling below 100 nm, achieving higher performance and packing more complex functionalities into digital integrated circuits have become easier. However, the scaling trend poses new challenges to design and process engineers. Such challenges include larger process parameter variations and the consequent parametric yield loss, ensuring the reliability of deep sub-micron technologies under soft errors, and reliably fabricating billions of devices on a die. The objective of my research has been to develop circuit and system level techniques to address process variations, transient errors, and the reliability concerns in deeply scaled CMOS technologies. The proposed techniques can be divided into three parts, highlighted in the next three sections. The first part addresses the issues related to process variations and proposes techniques to reduce the variation effects on power and performance. The second part proposes a novel low-overhead defect-tolerant approach for CMOS designs capable of efficiently recovering from dozens of defects. The third section deals with the transient errors and techniques to reduce the effect of transient errors with minimum hardware or computational overhead. 1. Variation-Tolerant Design With the increase of process parameter variations in CMOS technologies due to the processing and masking limitations, power and performance variations become major concerns of circuit designers. Techniques such as the use of forward/reverse body bias and voltage scaling are commonly used to bring down the delay and power consumption specifications in the acceptable range. Variation-aware circuit sizing is another technique used at the design stage to have a more variation-tolerant circuit. The key goal of this research is to provide techniques for designing more variation-tolerant circuits. We propose to attack the problem both at the design stage and at the post-fabrication stage. The latter requires the feasibility of having ways of specification tuning and a fast and efficient framework that makes the post-silicon tuning attractive. The summary of the proposed techniques is as follows: Variation-Aware Placement [1],[2]: In this work the huge leakage variation problem was addressed by looking at the effects that the gate placement have in leakage distribution. The work includes algorithms for the placement of gates in a dual-Vt circuit to mitigate the large leakage variation by reducing the variation caused by correlated within-die process variation. The experimental results on ISCAS benchmark circuits shows how by evenly distributing the low-Vt gates (which are more sensitive to variation sources such as the channel length variation) across a die, one could reduce the sub-threshold leakage variation as compared to the placement technique with the objective of minimizing wire length. The results show that the sub-threshold leakage variation is reduced by an average of 17% and maximum of 31%. This obtained with a small increase in wire length. Post-Manufacture Tuning Architecture [3]: In this work, an architectural framework for post-silicon performance testing and tuning to bring the delay of a die within the acceptable range was developed. Also, a modified form of CMOS gate that can be programmed to work in a low-speed or a high-speed mode is presented. In the proposed architecture, specific hardware tuning “knobs” (control mechanisms) such as tunable gates, supply voltage, or body bias can be employed to deal with the delay and leakage variation. These control mechanisms are actuated by a proposed efficient delay test method that implicitly measures the delay of embedded logic circuits. A hardware framework that can support such self-test/selfadaptation is developed and algorithms are designed for optimizing the various enabling design parameters. This work covers different area from delay testing to low-level This work was supported by NSF-ITR under award CCR-0220259 and by GSRC MARCO under award 2003-DT660. This work has not been presented in any other PhD forum. CMOS gate design of tunable gates. Simulation results show that using the proposed tunable gates on close-to-critical paths combined with the self-test/self-reconfiguration architecture can improve the delay yield by 40%. This is obtained with little increase in the power consumption 2. Defect-Tolerant CMOS Gate Design[4]. End-of-the-roadmap nano-scale CMOS is expected to suffer from significant defectivity due to manufacturing defects, random process variations, and wear-out. To ensure acceptable yield and reliable operation of the circuit during its life-time, future circuits must be equipped with a significant defect-tolerance capability. Traditional defecttolerance approaches are too expensive to be applied to general purpose circuits. This work proposes a defecttolerant CMOS logic gate architecture that exploits the inherent functional redundancy in the static CMOS. This is accomplished by reconfiguring the CMOS logic gate to a pseudo-NMOS-like gate in the presence of a defect. The proposed standard-cell-based defect-tolerant affects recovery in the presence of faulty transistors in the pull-up P-network by reconfiguring into a pseudo-NMOS gate, replacing the faulty P-network with a single P transistor as a resistive pull up. Similarly, a fault in the N-network is recovered from by replacing the N-network by a properly sized single N transistor. The proposed gate design can tolerate multiple defects in either the pull-up or pull-down network. To minimize the routing overhead associated with the reconfiguration, a grid-based two-dimensional routing methodology for control signals is proposed. The proposed control system can be implemented in the poly-silicon layer with virtually no adverse impact on the availability of the metal layers for the functional interconnects. The effectiveness of the proposed defect-tolerant technique and its impact on circuit delay and power is studied. It is shown that the technique imposes little delay overhead (less than 6%) but incurs leakage power dissipation overhead (less than 20%) in the presence of defects. 3. Probabilistic Checksum-Based Error